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| MC33201, MC33202, MC33204, NCV33202, NCV33204 Low Voltage, Rail-to-Rail Operational Amplifiers The MC33201/2/4 family of operational amplifiers provide rail-to-rail operation on both the input and output. The inputs can be driven as high as 200 mV beyond the supply rails without phase reversal on the outputs, and the output can swing within 50 mV of each rail. This rail-to-rail operation enables the user to make full use of the supply voltage range available. It is designed to work at very low supply voltages ( 0.9 V) yet can operate with a supply of up to +12 V and ground. Output current boosting techniques provide a high output current capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications. http://onsemi.com PDIP-8 P, VP SUFFIX CASE 626 8 1 SOIC-8 D, VD SUFFIX CASE 751 8 1 * Low Voltage, Single Supply Operation * * * * * * * * * (+1.8 V and Ground to +12 V and Ground) Input Voltage Range Includes both Supply Rails Output Voltage Swings within 50 mV of both Rails No Phase Reversal on the Output for Over-driven Input Signals High Output Current (ISC = 80 mA, Typ) Low Supply Current (ID = 0.9 mA, Typ) 600 W Output Drive Capability Extended Operating Temperature Ranges (-40 to +105C and -55 to +125C) Typical Gain Bandwidth Product = 2.2 MHz Pb-Free Packages are Available 8 1 Micro8] DM SUFFIX CASE 846A PDIP-14 P, VP SUFFIX CASE 646 14 1 SOIC-14 D, VD SUFFIX CASE 751A 1 14 14 1 TSSOP-14 DTB SUFFIX CASE 948G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 11 of this data sheet. (c) Semiconductor Components Industries, LLC, 2004 1 March, 2004 - Rev. 12 Publication Order Number: MC33201/D MC33201, MC33202, MC33204, NCV33202, NCV33204 PIN CONNECTIONS MC33201 All Case Styles NC 1 2 Inputs 3 VEE 4 6 5 Output NC Inputs 2 8 7 NC VCC Output 1 1 2 Inputs 1 3 1 4 MC33204 All Case Styles 14 Output 4 13 12 11 10 2 3 Inputs 4 VEE Inputs 3 Output 3 VCC 4 5 6 (Top View) MC33202 All Case Styles Output 1 1 2 Inputs 1 3 VEE 4 2 1 9 8 Output 2 7 (Top View) VCC Output 2 8 7 6 Inputs 2 5 (Top View) VCC VCC VCC Vin - VEE Vout Vin + VCC VEE This device contains 70 active transistors (each amplifier). Figure 1. Circuit Schematic (Each Amplifier) http://onsemi.com 2 MC33201, MC33202, MC33204, NCV33202, NCV33204 MAXIMUM RATINGS Rating Supply Voltage (VCC to VEE) Input Differential Voltage Range Common Mode Input Voltage Range (Note 2) Output Short Circuit Duration Maximum Junction Temperature Storage Temperature Maximum Power Dissipation Symbol VS VIDR VCM ts TJ Tstg PD Value +13 Note 1 VCC + 0.5 V to VEE - 0.5 V Note 3 +150 - 65 to +150 Note 3 Unit V V V sec C C mW DC ELECTRICAL CHARACTERISTICS (TA = 25C) Characteristic Input Offset Voltage VIO (max) MC33201 MC33202, NCV33202 MC33204 Output Voltage Swing VOH (RL = 10 kW) VOL (RL = 10 kW) Power Supply Current per Amplifier (ID) VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit mV 8.0 10 12 1.9 0.10 1.125 8.0 10 12 3.15 0.15 1.125 6.0 8.0 10 4.85 0.15 1.125 Vmin Vmax mA Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND. DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25C, unless otherwise noted.) Characteristic Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V) MC33201: TA = + 25C MC33201: TA = - 40 to +105C MC33201V: TA = - 55 to +125C MC33202: TA = + 25C MC33202: TA = - 40 to +105C MC33202V: TA = - 55 to +125C NCV33202V: TA = - 55 to +125C (Note 4) MC33204: TA = + 25C MC33204: TA = - 40 to +105C MC33204V: TA = - 55 to +125C Input Offset Voltage Temperature Coefficient (RS = 50 W) TA = - 40 to +105C TA = - 55 to +125C Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) TA = + 25C TA = - 40 to +105C TA = - 55 to +125C Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) TA = + 25C TA = - 40 to +105C TA = - 55 to +125C Common Mode Input Voltage Range Figure 3 Symbol VIO - - - - - - - - - - 4 DVIO/DT - - 5, 6 IIB - - - - IIO - - - - VICR VEE 5.0 10 - - 50 100 200 VCC V 80 100 - 200 250 500 nA 2.0 2.0 - - nA - - - - - - - - - 6.0 9.0 13 8.0 11 14 14 10 13 17 mV/C Min Typ Max Unit mV 1. The differential input voltage of each amplifier is limited by two internal parallel back-to-back diodes. For additional differential input voltage range, use current limiting resistors in series with the input pins. 2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage on either input must not exceed either supply rail by more than 500 mV. 3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2) 4. NCV33202 and NCV33204 are qualified for automotive use. http://onsemi.com 3 MC33201, MC33202, MC33204, NCV33202, NCV33204 DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25C, unless otherwise noted.) Characteristic Large Signal Voltage Gain (VCC = + 5.0 V, VEE = - 5.0 V) RL = 10 kW RL = 600 W Output Voltage Swing (VID = 0.2 V) RL = 10 kW RL = 10 kW RL = 600 W RL = 600 W Common Mode Rejection (Vin = 0 V to 5.0 V) Power Supply Rejection Ratio VCC/VEE = 5.0 V/GND to 3.0 V/GND Output Short Circuit Current (Source and Sink) Power Supply Current per Amplifier (VO = 0 V) TA = - 40 to +105C TA = - 55 to +125C Figure 7 Symbol AVOL 50 25 8, 9, 10 VOH VOL VOH VOL 11 12 13, 14 15 CMR PSRR 500 ISC ID - - 0.9 0.9 1.125 1.125 50 25 80 - - mA mA 4.85 - 4.75 - 60 4.95 0.05 4.85 0.15 90 - 0.15 - 0.25 - dB mV/V 300 250 - - V Min Typ Max Unit kV/V AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25C, unless otherwise noted.) Characteristic Slew Rate (VS = 2.5 V, VO = - 2.0 V to + 2.0 V, RL = 2.0 kW, AV = +1.0) Gain Bandwidth Product (f = 100 kHz) Gain Margin (RL = 600 W, CL = 0 pF) Phase Margin (RL = 600 W, CL = 0 pF) Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) Power Bandwidth (VO = 4.0 Vpp, RL = 600 W, THD 1 %) Total Harmonic Distortion (RL = 600 W, VO = 1.0 Vpp, AV = 1.0) f = 1.0 kHz f = 10 kHz Open Loop Output Impedance (VO = 0 V, f = 2.0 MHz, AV = 10) Differential Input Resistance (VCM = 0 V) Differential Input Capacitance (VCM = 0 V) Equivalent Input Noise Voltage (RS = 100 W) f = 10 Hz f = 1.0 kHz Equivalent Input Noise Current f = 10 Hz f = 1.0 kHz 25 24 Figure 16, 26 17 20, 21, 22 20, 21, 22 23 Symbol SR 0.5 GBW AM OM CS BWP THD - - ZO - Rin Cin en - - 25 in - - 0.8 0.2 - - 25 20 - - - - 100 200 8.0 - - - kW pF nV/ Hz pA/ Hz 0.002 0.008 - - W - - - - - 1.0 2.2 12 65 90 28 - - - - - - MHz dB Deg dB kHz % Min Typ Max Unit V/ms http://onsemi.com 4 MC33201, MC33202, MC33204, NCV33202, NCV33204 PD(max) , MAXIMUM POWER DISSIPATION (mW 2500 8 and 14 Pin DIP Pkg 2000 1500 1000 500 SOIC-8 Pkg TSSOP-14 Pkg SO-14 Pkg PERCENTAGE OF AMPLIFIERS (%) 40 35 30 25 20 15 10 5.0 0 -10 - 8.0 - 6.0 - 4.0 - 2.0 0 2.0 4.0 6.0 VIO, INPUT OFFSET VOLTAGE (mV) 8.0 10 360 amplifiers tested from 3 (MC33204) wafer lots VCC = + 5.0 V VEE = Gnd TA = 25C DIP Package 0 - 55 - 40 - 25 0 25 50 85 TA, AMBIENT TEMPERATURE (C) 125 Figure 2. Maximum Power Dissipation versus Temperature Figure 3. Input Offset Voltage Distribution 50 40 PERCENTAGE OF AMPLIFIERS (%) 30 20 10 0 - 50 - 40 - 30 - 20 360 amplifiers tested from 3 (MC33204) wafer lots VCC = + 5.0 V VEE = Gnd TA = 25C DIP Package 200 I IB , INPUT BIAS CURRENT (nA) VCC = + 5.0 V VEE = Gnd 160 120 80 VCM > 1.0 V 40 0 - 55 - 40 - 25 VCM = 0 V to 0.5 V -10 0 10 20 30 40 50 0 25 70 85 125 TCV , INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/C) IO TA, AMBIENT TEMPERATURE (C) Figure 4. Input Offset Voltage Temperature Coefficient Distribution Figure 5. Input Bias Current versus Temperature A VOL , OPEN LOOP VOLTAGE GAIN (kV/V) 150 I IB , INPUT BIAS CURRENT (nA) 100 50 0 - 50 -100 -150 - 200 - 250 0 VCC = 12 V VEE = Gnd TA = 25C 2.0 4.0 6.0 8.0 10 VCM, INPUT COMMON MODE VOLTAGE (V) 12 300 260 220 180 140 VCC = + 5.0 V VEE = Gnd RL = 600 W DVO = 0.5 V to 4.5 V 0 25 70 85 TA, AMBIENT TEMPERATURE (C) 105 125 100 - 55 - 40 - 25 Figure 6. Input Bias Current versus Common Mode Voltage Figure 7. Open Loop Voltage Gain versus Temperature http://onsemi.com 5 MC33201, MC33202, MC33204, NCV33202, NCV33204 12 VO, OUTPUT VOLTAGE (Vpp ) 10 8.0 6.0 4.0 2.0 0 1.0 2.0 3.0 4.0 5.0 VCC,VEE SUPPLY VOLTAGE (V) 6.0 RL = 600 W TA = 25C VSAT, OUTPUT SATURATION VOLTAGE (V) VCC TA = - 55C TA = 125C TA = 25C VCC - 0.2 V VCC - 0.4 V VEE + 0.4 V TA = 25C TA = - 55C 0 5.0 10 IL, LOAD CURRENT (mA) 15 VEE + 0.2 V VEE 20 VCC = + 5.0 V VEE = - 5.0 V TA = 125C Figure 8. Output Voltage Swing versus Supply Voltage Figure 9. Output Saturation Voltage versus Load Current CMR, COMMON MODE REJECTION (dB) 12 VO, OUTPUT VOLTAGE (Vpp ) 100 80 60 40 20 0 VCC = + 6.0 V VEE = - 6.0 V TA = - 55 to +125C 9.0 6.0 VCC = + 6.0 V VEE = - 6.0 V RL = 600 W AV = +1.0 TA = 25C 10 k 100 k f, FREQUENCY (Hz) 1.0 M 3.0 0 1.0 k 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M Figure 10. Output Voltage versus Frequency Figure 11. Common Mode Rejection versus Frequency PSR, POWER SUPPLY REJECTION (dB) 120 100 PSR+ 80 60 PSR- 40 20 0 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M VCC = + 6.0 V VEE = - 6.0 V TA = - 55 to +125C I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) 100 Source 80 60 Sink 40 20 0 VCC = + 6.0 V VEE = - 6.0 V TA = 25C 0 1.0 2.0 3.0 4.0 5.0 6.0 Vout, OUTPUT VOLTAGE (V) Figure 12. Power Supply Rejection versus Frequency Figure 13. Output Short Circuit Current versus Output Voltage http://onsemi.com 6 MC33201, MC33202, MC33204, NCV33202, NCV33204 I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) I CC , SUPPLY CURRENT PER AMPLIFIER (mA) 150 VCC = + 5.0 V VEE = Gnd 2.0 1.6 TA = 125C 1.2 TA = 25C 0.8 TA = - 55C 0.4 0 0 125 100 75 50 25 0 - 55 - 40 - 25 Source Sink 0 25 70 85 TA, AMBIENT TEMPERATURE (C) 105 125 1.0 2.0 3.0 4.0 5.0 VCC, VEE, SUPPLY VOLTAGE (V) 6.0 Figure 14. Output Short Circuit Current versus Temperature Figure 15. Supply Current per Amplifier versus Supply Voltage with No Load SR, SLEW RATE (V/ s) 1.5 VCC = + 2.5 V VEE = - 2.5 V VO = 2.0 V GBW, GAIN BANDWIDTH PRODUCT (MHz) 2.0 4.0 VCC = + 2.5 V VEE = - 2.5 V f = 100 kHz 3.0 +Slew Rate 1.0 -Slew Rate 0.5 2.0 1.0 0 - 55 - 40 - 25 0 25 70 85 105 125 0 - 55 - 40 - 25 0 25 70 85 105 125 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 16. Slew Rate versus Temperature Figure 17. Gain Bandwidth Product versus Temperature , OPEN LOOP VOLTAGE GAIN (dB) VOL O , EXCESS PHASE (DEGREES) 50 80 120 1A 50 30 80 120 160 30 10 1A - Phase, CL = 0 pF 1B - Gain, CL = 0 pF 2A - Phase, CL = 300 pF 2B - Gain, CL = 300 pF 100 k f, FREQUENCY (Hz) 1.0 M 2A 2B 1B 1A 2A 160 200 240 10 M 10 1A - Phase, VS = 6.0 V 1B - Gain, VS = 6.0 V 2A - Phase, VS = 1.0 V 2B - Gain, VS = 1.0 V 100 k f, FREQUENCY (Hz) 2B 1B -10 -10 200 240 10 M A - 30 10 k - 30 10 k 1.0 M Figure 18. Voltage Gain and Phase versus Frequency Figure 19. Voltage Gain and Phase versus Frequency http://onsemi.com 7 O , EXCESS PHASE (DEGREES) VS = 6.0 V TA = 25C RL = 600 W A VOL, OPEN LOOP VOLTAGE GAIN (dB) 70 40 70 CL = 0 pF TA = 25C RL = 600 W 40 MC33201, MC33202, MC33204, NCV33202, NCV33204 70 Phase Margin O M , PHASE MARGIN (DEGREES) O M , PHASE MARGIN (DEGREES) 60 50 40 30 20 10 0 - 55 - 40 - 25 Gain Margin 0 25 70 85 105 TA, AMBIENT TEMPERATURE (C) VCC = + 6.0 V VEE = - 6.0 V RL = 600 W CL = 100 pF 60 A , GAIN MARGIN (dB) M 50 40 30 20 10 0 125 60 45 30 15 0 10 100 1.0 k 10 k RT, DIFFERENTIAL SOURCE RESISTANCE (W) VCC = + 6.0 V VEE = - 6.0 V TA = 25C 70 75 Phase Margin 75 60 45 30 15 0 100 k A , GAIN MARGIN (dB) M i n , INPUT REFERRED NOISE CURRENT (pA/ Hz) Gain Margin Figure 20. Gain and Phase Margin versus Temperature Figure 21. Gain and Phase Margin versus Differential Source Resistance 80 O M , PHASE MARGIN (DEGREES) 70 60 50 40 30 20 10 0 10 100 CL, CAPACITIVE LOAD (pF) Gain Margin Phase Margin VCC = + 6.0 V VEE = - 6.0 V RL = 600 W AV = 100 TA = 25C 16 CS, CHANNEL SEPARATION (dB) 14 A , GAIN MARGIN (dB) M 12 10 8.0 6.0 4.0 2.0 0 1.0 k 150 120 90 60 30 0 100 VCC = + 6.0 V VEE = - 6.0 V VO = 8.0 Vpp TA = 25C 1.0 k f, FREQUENCY (Hz) 10 k AV = 10 AV = 100 Figure 22. Gain and Phase Margin versus Capacitive Load Figure 23. Channel Separation versus Frequency THD, TOTAL HARMONIC DISTORTION (%) 10 en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz) 1.0 VCC = + 5.0 V TA = 25C VO = 2.0 Vpp AV = 1000 VEE = - 5.0 V RL = 600 W 50 40 30 20 10 Noise Current 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k Noise Voltage VCC = + 6.0 V VEE = - 6.0 V TA = 25C 5.0 4.0 3.0 2.0 1.0 0 100 k 0.1 AV = 100 AV = 10 0.01 AV = 1.0 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 0.001 10 Figure 24. Total Harmonic Distortion versus Frequency Figure 25. Equivalent Input Noise Voltage and Current versus Frequency http://onsemi.com 8 MC33201, MC33202, MC33204, NCV33202, NCV33204 DETAILED OPERATING DESCRIPTION General Information The MC33201/2/4 family of operational amplifiers are unique in their ability to swing rail-to-rail on both the input and the output with a completely bipolar design. This offers low noise, high output current capability and a wide common mode input voltage range even with low supply voltages. Operation is guaranteed over an extended temperature range and at supply voltages of 2.0 V, 3.3 V and 5.0 V and ground. Since the common mode input voltage range extends from VCC to VEE, it can be operated with either single or split voltage supplies. The MC33201/2/4 are guaranteed not to latch or phase reverse over the entire common mode range, however, the inputs should not be allowed to exceed maximum ratings. Circuit Information Rail-to-rail performance is achieved at the input of the amplifiers by using parallel NPN-PNP differential input stages. When the inputs are within 800 mV of the negative rail, the PNP stage is on. When the inputs are more than 800 mV greater than VEE, the NPN stage is on. This switching of input pairs will cause a reversal of input bias currents (see Figure 6). Also, slight differences in offset voltage may be noted between the NPN and PNP pairs. Cross-coupling techniques have been used to keep this change to a minimum. In addition to its rail-to-rail performance, the output stage is current boosted to provide 80 mA of output current, enabling the op amp to drive 600 W loads. Because of this high output current capability, care should be taken not to exceed the 150C maximum junction temperature. V , OUTPUT VOLTAGE (2.0 mV/DIV) O t, TIME (5.0 ms/DIV) V , OUTPUT VOLTAGE (50 mV/DIV) O VCC = + 6.0 V VEE = - 6.0 V RL = 600 W CL = 100 pF TA = 25C VCC = + 6.0 V VEE = - 6.0 V RL = 600 W CL = 100 pF TA = 25C t, TIME (10 ms/DIV) Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response V , OUTPUT VOLTAGE (2.0 V/DIV) O VCC = + 6.0 V VEE = - 6.0 V RL = 600 W CL = 100 pF AV = 1.0 TA = 25C t, TIME (10 ms/DIV) Figure 28. Large Signal Transient Response Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. http://onsemi.com 9 MC33201, MC33202, MC33204, NCV33202, NCV33204 ORDERING INFORMATION Operational Amplifier Function Single Device MC33201D MC33201DR2 MC33201P MC33201VD Dual MC33202D MC33202DG MC33202DR2 MC33202DR2G Dual MC33202DMR2 MC33202P MC33202VD MC33202VDR2 NCV33202VDR2* MC33202VP Quad MC33204D MC33204DR2 MC33204DTB MC33204DTBR2 MC33204P MC33204VD MC33204VDR2 NCV33204DR2* NCV33204DTBR2* MC33204VP TA = -55 to 125C TA= -40 to +105C TA = -55 to 125C TA= -40 to +105C TA = -55 to 125C TA= -40 to +105C Operating Temperature Range TA= -40 to +105C Package SOIC-8 SOIC-8 PDIP-8 SOIC-8 SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) Micro-8 PDIP-8 SOIC-8 SOIC-8 SOIC-8 PDIP-8 SO-14 SO-14 TSSOP-14 TSSOP-14 PDIP-14 SO-14 SO-14 SO-14 TSSOP-14 PDIP-14 4000 Units / Tape & Reel 50 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 50 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 25 Units / Rail 2500 Units / Tape & Reel Shipping 98 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail 98 Units / Rail 98 Units / Rail *NCV33202 and NCV33204 are qualified for automotive use. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 MC33201, MC33202, MC33204, NCV33202, NCV33204 MARKING DIAGRAMS SOIC-8 D SUFFIX CASE 751 8 3320x ALYW 1 1 SOIC-8 VD SUFFIX CASE 751 8 320xV ALYW 8 PDIP-8 P SUFFIX CASE 626 8 MC3320xP AWL YYWW 1 PDIP-14 P SUFFIX CASE 646 14 MC33204VD AWLYWW 1 14 MC33204P AWLYYWW 1 1 x = 1 or 2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week *This marking diagram applies to NCV3320x 1 MC33204VP AWLYYWW 1 PDIP-14 VP SUFFIX CASE 646 14 MC33 204 ALYW 1 MC33202VP AWL YYWW 1 PDIP-8 VP SUFFIX CASE 626 Micro-8 DM SUFFIX CASE 846A 8 3202 AYW 1 TSSOP-14 DTB SUFFIX CASE 948G 14 MC33 204V ALYW SO-14 D SUFFIX CASE 751A 14 MC33204D AWLYWW * SO-14 VD SUFFIX CASE 751A 14 * * http://onsemi.com 11 MC33201, MC33202, MC33204, NCV33202, NCV33204 PACKAGE DIMENSIONS PDIP-8 P, VP SUFFIX CASE 626-05 ISSUE L NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 8 5 -B- 1 4 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M http://onsemi.com 12 MC33201, MC33202, MC33204, NCV33202, NCV33204 SOIC-8 D, VD SUFFIX CASE 751-07 ISSUE AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 -X- A 8 5 B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches SOIC-8 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 13 MC33201, MC33202, MC33204, NCV33202, NCV33204 PACKAGE DIMENSIONS -A- Micro8 DM SUFFIX CASE 846A-02 ISSUE F K -B- PIN 1 ID G D 8 PL 0.08 (0.003) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --- 1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --- 0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028 TB S A S -T- PLANE 0.038 (0.0015) H STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SEATING C J STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. L SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 8X 3.20 0.126 4.24 0.167 5.28 0.208 6X 0.65 0.0256 SCALE 8:1 mm inches Micro8E *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MC33201, MC33202, MC33204, NCV33202, NCV33204 PACKAGE DIMENSIONS PDIP-14 P, VP SUFFIX CASE 646-06 ISSUE M 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 A F N -T- SEATING PLANE L C K H G D 14 PL 0.13 (0.005) M J M DIM A B C D F G H J K L M N SOIC-14 D, VD SUFFIX CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 -A- 14 8 -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J http://onsemi.com 15 MC33201, MC33202, MC33204, NCV33202, NCV33204 PACKAGE DIMENSIONS TSSOP-14 DTB SUFFIX CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 16 EE CC EE CC MC33201/D |
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